FYI...
Hi All,
Please be a part of expansion by joining or referring your friends to Mirafra Family.
We are looking for people working in Verification, Physical design using ( Talus, ICC or SOC Encounter ) and STA Synthesis for India and US.
Following are the reqs.: (Detailed JDs below)
1. Physical Design (Engineer/Lead/Manager, 4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
2. Verification using System Verilog (4-8 yrs.)
Detailed JDs
1. Physical Design Engineer/Lead/Manager (4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD activities involve , Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints management , floorplan/IR-Drop/placement/
Optimization/Timing Closure/DRC/LVS .
2. System Verilog verification.
FE verification (OVM) engineer openings,experience ranging from 4 to 8 yrs.
1. Experience in RTL verification and fundamental knowledge in basic verification concepts and issues
2. Hands on experience in RTL verification using OVM
3. Development of OVCs using System Verilog
4. Working experience in OVM verification environment building and integration
5. Developing C/C+ testcases .
6. Working knowledge on ARM based design verification, knowhow of AHB/APB bus protocols.
3. STA
4. Formal Verification (LEC and/or Formality)
5. Synthesis
6. Low power domain verification (Spyglass)
7. CDC (clock domain crossing)
8. IR drop analysis (Redhawk)
9. Physical Verification (Calibre)
10. PNR (Atoptech)
Please share your updated profile to naveenyk@mirafra.com
Wish you all the best
Hi All,
Please be a part of expansion by joining or referring your friends to Mirafra Family.
We are looking for people working in Verification, Physical design using ( Talus, ICC or SOC Encounter ) and STA Synthesis for India and US.
Following are the reqs.: (Detailed JDs below)
1. Physical Design (Engineer/Lead/Manager, 4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
2. Verification using System Verilog (4-8 yrs.)
Detailed JDs
1. Physical Design Engineer/Lead/Manager (4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD activities involve , Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints management , floorplan/IR-Drop/placement/
Optimization/Timing Closure/DRC/LVS .
2. System Verilog verification.
FE verification (OVM) engineer openings,experience ranging from 4 to 8 yrs.
1. Experience in RTL verification and fundamental knowledge in basic verification concepts and issues
2. Hands on experience in RTL verification using OVM
3. Development of OVCs using System Verilog
4. Working experience in OVM verification environment building and integration
5. Developing C/C+ testcases .
6. Working knowledge on ARM based design verification, knowhow of AHB/APB bus protocols.
3. STA
4. Formal Verification (LEC and/or Formality)
5. Synthesis
6. Low power domain verification (Spyglass)
7. CDC (clock domain crossing)
8. IR drop analysis (Redhawk)
9. Physical Verification (Calibre)
10. PNR (Atoptech)
Please share your updated profile to naveenyk@mirafra.com
Wish you all the best
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