Thursday, December 31, 2015
Change Pond Openings for Front End,Web Developer and Java positions
Wednesday, December 30, 2015
Friday, December 4, 2015
Walk-In Drive for Freshers on 5/12/2015@Madhees
Madhees hiring graduates for our Research Coding Team in Hyderabad.
- Any Non-Technical Graduate(B.com/B.Sc/B.A)
- Hands on experience on Computer (Typing speed – 25 wpm)
- Any Training Certificate in computer (Desirable)
- Good Communication and Interpersonal skills (Must)
S .Chandra Reddy Towers
100 Ft Road,
Ayappa Society,
Madhapur
Friday, November 6, 2015
TCS Walkin registraiton for Freshers
Monday, October 26, 2015
PYTHON DEVELOPER with 4+ years Exp for Hyderabad location
Thursday, October 8, 2015
Freshers Openings for 2015 passout with GlobalLogic Bangalore location
Tuesday, September 15, 2015
Java Developer Openings with Value Labs for Hyderabad Location
Company: ValueLabs.
Location: Hyderabad / Secunderabad
Website: http://www.valuelabs.com
Eligibility: Any Graduate
Click to assess yourself on the required skill before applying!
Skills: Struts , Java , Core Java, Spring, J2EE , Hibernate , Web Services, Restful.
Experience: 4 - 8 Years
Job Summary:
Experience: 4 to 8 yrs
Job Title: Sr. Software Engineer / System Analyst.
Work Location: ValueLabs, Hyderabad.
Responsibilities:
4+ Years of experience with Java
Very Strong with Core Java Skills
Good experience with Spring/Struts/Hibernate
Experience with Web Services
Team player with excellent communication skills.
If you would be interested with the above job opportunity revert with your updated profile along with the following details ASAP:
1. Full Name:
2. Contact Number:
3. Current Organization:
4. Current Location:
5. Total Exp:
6. Relevant Exp:
7. Current CTC:
8. Exp CTC:
9. Notice Period:
Contact:
Contact Person: Geethika G
Email: geethika.gummadi@valuelabs.com
Address: Plot # 41, Survey # 64, Hitec City, Lane adjacent to Cyber Gateway, Opp. Oracle, Hyderabad, Andhra Pradesh, India 500081.
Telephone: 91-40-66239000
Posted Date: Sep 15, 2015
Tuesday, September 8, 2015
Sysparms looking for part time java developers
Wish you all the best
-CareersValleyinfoTeam
Tuesday, July 14, 2015
Freshers Openings with Deloitte for Hyderabad Location
SQL Server Administrator Openings with CERNER HEALTHCARE SOLUTIONS PVT LTD for Bangalore location
Job Title: | SQL Server Administrator | |
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Company: | CERNER HEALTHCARE SOLUTIONS PVT LTD | |
Location: | Bangalore | |
Website: | http://www.cerner.com | |
Eligibility: | Any Graduate |
Skills: | Ms Sql Server , Performance Tuning, Database Design, Database Administration |
---|---|
Experience: | 2 - 5 Years |
Job Summary: |
Responsibities:
The Database Administrator is responsible for the installation of the database environment and outputs. The DBA performs work on new project installations, Database release upgrades, and/or database performance management projects.
Work involves interaction with end customers and Installation and Support teams, troubleshooting of customer issues, providing solutions.
Build, manage and administration of database environments.
MS SQL Server Database Backups/Restores, Installations /Upgradations /Migrations/Configurations, High Availability configurations, Performance Tuning, Database Design, Disaster Recovery support
Work also involves interaction with end customers and Installation and Support teams, troubleshooting of customer issues, providing solutions.
Work might demand extended working hours / weekend support and might require working in Shifts.
Monitor & troubleshoot databases, alerts, backups and performance issues
Ability to multitask and work on multiple projects simultaneously.
Ability to learn new processes, tools and technologies as required.
Ability to work overtime and irregular hours as and when needed.
Strong organizational skills.
Active team player, collaborate well with global teams.
NOTE: Work might demand extended working hours / weekend support and might require working in Shifts.
Requirements:
Bachelor's degree or equivalent experience
2 to 5 years of experience in providing 24x7 production database support and project implementations
Strong SQL Server 2008/12/14 DBA Experience is essential
Hands on experience on System DBA tasks, TSQL Programming, High Availability, Performance Tuning, Disaster Recovery, SQL Server Architecture is required.
Strong technically oriented background
Experience with RDBMS technologies: Predominantly in SQL Server. Knowledge on DB2 or Oracle would be an added advantage
SQL Server certifications are preferred.
Familiar with any change and problem management process.
Experience working independently with minimal supervision.
Display flexibility and openness to listen to and evaluate a variety of opinions and approaches.
Requires strong English communications. Requires customer relationship skills (professional & polished). Ability to diagnose & troubleshoot problems, and suggest solutions and improvements.
Soarian Knowledge a Plus.
Please share your resumes to manjusha.dash@cerner.com |
Java/Android Developer for Bangalore location
Job Title: | Java/Android Developer | |
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Company: | India Brains Infotech | |
Location: | Bangalore | |
Website: | ||
Eligibility: | Any Graduate |
Skills: | Core Java , Android SDK, Javascript ,android application, iphone application |
---|---|
Salary: | 2,50,000 - 5,50,000 P.A. |
Experience: | 2-4 years |
Job Summary: |
Responsibilities:
1.Design, develop and build the native applications for Android platform
2.Work closely with web development team (PHP) to create mobile applications linked with
3.SQL databases
Requirements:
1.Minimum B.E. / B.Tech / MCA / M.Sc in Computers / IT with 4+ years of experience in Android development.
2.Strong experience in Core Java, Android SDK , Web Services, SQLite and third part APIs such as Google Map, Social media
integration
3.Icloud integration.
4.Preferably should have published one or more Android apps in the Google Play store.
5.Solid understanding of the full mobile development life cycle.
|
Monday, June 1, 2015
JOB - Semiconductor (RTL2GDSII, STD CELL Layout, Physical Design, STA Synthesis, SoC/IP/ ASIC Verification). DETAILS BELOW.
Skill language is added advantage. Good fundamental concept on Finfet, CMOS transistors
Good knowledge of semi-custom design flows.
we are looking for an experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems. The engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools.
Fully responsible for Netlist to GDS physical design implementation of complex chips/blocks.
Fully responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team.
Fully responsible of physical implementation and schedule planning
Interact with physical and digital design teams between Singapore and Taiwan.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience
Similar company work experience
Has implemented large blocks with more than 30% area with memories.
Good at design closure (congestion, timing and physical verification)
Block/Chip PD: exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm...). Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing methodology, constraints definition/cleanup. Desired experience using Synopsys PT
Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM.
>Experience in develop, support & maintain physical design flows & methodologies
>Experience in PTSI, ICC/First Encounter/EDI, Nanoroute, Calibre, StarRC, & Conformal
> Good knowledge of standard cell libraries
> Hands-on with STA, EM/IR & sign-off flows
>Expertise in handling highspeed digital design will be an added advantage.
> Minimum 4 years Hands-on experience with:
1. Floor planning, place & route, power & clock distribution, pin placement & timing constraints generation.
2. Timing convergence using high speed design techniques
3. Physical design verification.
4. Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods. Prior experience with 40nm or finer geometries.
For the position of IP Verification Engineer the following qualifications must be met:
5+ years of experience on IP Verification.
Developed the test benches using the System Verilog, UVM or Specman/eRM.
Developed the BFM/VIP using System Verilog or UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Understanding of Cache Concepts is desirable.
Knowledge of USB/PCIE/DDR protocols is preferred.
We are looking for a SoC Verification Engineer with the Following Qualifications:
5+ years of experience on SoC Verification
Developed the test benches using the System Verilog and UVM.
Knowledge of C-based Verification is preferred
should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage goals.
Working knowledge of Power Aware RTL and Gate Level Simulation.
Understanding of ARM Core and DDR/LPDDR is preferable.
PCIe, USB, Serial Peripheral knowledge is preferred.
Design and develop automation utilities and support verification activities. Senior ASIC/SoC Verification engineer needs to closely work with the Verification lead and ASIC/SoC architects in defining and developing the verification environment. Desired Skills and Experience.
o5+ years of experience on IP and/or SoC Verification
excellent knowledge of Verilog/VHDL/SV
developed the test benches using the System Verilog and UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Working knowledge of Power Aware RTL and Gate Level Simulation is preferable.
Understanding of ARM Core and DDR/LPDDR is preferable.
Knowledge of C/C++-based Verification is preferred.
High Speed interface PCIe, USB, Serial Peripheral knowledge is preferred.
oFPGA knowledge is a value add
good communication skills and Team player.
Knowledge on the ARM 64 bit V8 Architecture
Good Expertise on the DDR I/f and DDR Phys. Working Knowledge on the DDR3 and DDR4 Protocols (or)
Good Expertise on the USB2.0 and USB3.0 Protocols.
Requirement for RTL designers. (J.D)
looking for smart and enterprising RTL / ASIC Design Engineers with following skills:
* Hands on experience in RTL Design, Logic Design, and Micro-architecture development.
* Strong knowledge in HDL (Verilog/VHDL).
* Experience with Linting, Clock domain crossing checks required.
* Good understanding of Verification flows, including System Verilog.
* Good understanding of Synthesis, Static Timing Analysis, Equivalence Checking.
* Strong oral and written communication skills.
Responsibilities:
Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity).
Monday, May 25, 2015
MUMPs opening for chennai location
Hi,
We are currently hiring MUMPs Developer for our Bangalore and Chennai Office.
Please find the JD below:
Work Location- Bangalore/Chennai
Experience-2-10 Years
Mandatory Skills :-
- Resource should have worked either on C++ or Java or MUMPS/CACHE
- Resource should have strong experience in OOPS concept
- Resource will be working as a Individual contributor
- Resource should have good attitude
- Resource should have interest to write“Profile Scripting Language”(PSL Scripting)
- Resource should open for both Chennai and Bangalore location
- Experience in Banking Domain will be an added advantage
Send your resumes to pmsuga@gmail.com
Hi,
We are currently hiring MUMPs Developer for our Bangalore and Chennai Office.
Please find the JD below:
Work Location- Bangalore/Chennai
Experience-2-10 Years
Mandatory Skills :-
- Resource should have worked either on C++ or Java or MUMPS/CACHE
- Resource should have strong experience in OOPS concept
- Resource will be working as a Individual contributor
- Resource should have good attitude
- Resource should have interest to write“Profile Scripting Language”(PSL Scripting)
- Resource should open for both Chennai and Bangalore location
- Experience in Banking Domain will be an added advantage
Thanks
Murali
• | • | • |
Thanks
Murali
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