Please find various job descriptions below and let us know if you would like to know more.
Your profile will be kept confidential and only be shared with clients after a telephonic discussion and a thorough interest check.
About the company: It’s a Product Based Semiconductor Company, Founded 12 Years ago, Headquarter at the USA, Branches at Bangalore, Netherlands, Taiwan, Canada.
Position: Permanent with this product company.
Job location: South Bangalore.
- Analog Layout Design Engineers: 8+Yrs.
Ø Responsibilities:
- Layout engineer specializing in custom deep submicron Analog layout.
- Interface with Design Engineers from various locations to provide feedback and implement enhancements to endure design correctness and robustness.
- Participate in layout reviews across various teams.
- Work within a team framework
- May involve some traveling to other design sites
Ø Requirements:
- The candidate must have a B.E. (Electronics) degree. M.E. / M. Tech (Electronics/Microelectronics) preferred.
- Experience in Custom Analog Layout and Integration is a must.
- The candidate must have at least 5-10 years of relevant experience.
- Experience with GF 14nm nodes and below.
- Understand issues involved in high speed analog layouts.
- Experience with Cadence design tools and Calibre/PVS verification tools.
- Good communication skills
- Skill scripting is a plus
- DIGITAL DESIGN LEAD (RTL+DSP centric) preferably 15+Yrs.
Ø Responsibilities:
• Responsible for leading next generation network controller ASICs and/or digital portions of mixed signal SoCs from specification, implementation, verification, through full-chip sign-off, and bring-up. You will lead a team of digital designers as well as have cross functional integration responsibilities requiring both depth and breadth in semiconductor design.
Ø Requirements:
• Full understanding of digital design methodologies and tools including RTL coding in Verilog, simulation, synthesis, static timing analysis, and formal verification.
• Expertise in ASIC design flows for deep sub-micron technologies.
• Desirable to have experience in: Ethernet, digital signal processing implementation, or networking technologies.
• Must have experienced multiple ASIC tape-outs from concept to full production.
• Must have excellent English written and verbal communication and interpersonal skills.
Ø Education & Experience:
• BS or MS (preferred) in Electrical Engineering;
• Minimum 15+ years of design experience
- Digital Design Verification Engineer (8-15) Yrs.
Ø Responsibilities:
8+ years of DV experience in building and architecting verification environments, preferably from scratch for multiple projects.
The engineer should have experience in writing testplan, creating & enhancing verification environments and be comfortable coding any portion of a test bench (models, checkers, scoreboards, coverage monitors, etc.).
Candidate should have experience in the development of constraint random DV environments for large ASIC blocks.
Ø Qualifications:
· Languages: Must have experience in Verilog/SystemVerilog.
· Experience with C++ is a plus.
· Methodology: Strong UVM (must) and Specman (is a plus).
· Experience with gate level simulation and debug.
· Scripting: Perl, Python.
· Experience with PCIe and/or networking (Ethernet) protocol is a plus.
· Experience with SoC verification is a plus.
· Good interpersonal/communication skill.
· Experience in assertion methodology, emulation/hardware acceleration platforms is a plus.
Ø Working experience in Network interface controllers, descriptor based DMA engines, Ethernet filter/parser.
Ø Please note - SoC verification is only a plus point since we are not doing any heavy SoC related verification.
Ø For 12+ years of experience, we are very particular about his/her very good domain knowledge with at least two the following.
- PCIe (GEN3/4)
- Descriptor based DMA engines
- Ethernet filter/Parser
Ø Company is looking for someone who has experience with Network Interface controller that talks to the host processor via PCIe (GEN3/GEN4) bus.
- Digital Design Engineer/Senior Digital Design Engineer: 8+Yrs.
Ø Responsibilities:
Ø Develop key blocks of logic in a next generation physical layer/mixed signal SOCs
Ø Perform hardware feasibility analysis and come up with a micro-architecture specification helping it map to a high performance, implementable design
Ø Work with verification, DFT, synthesis, circuits, backend implementation teams to realize quality implementation
Ø Requirements:
Ø Minimum BE/BS degree in Electrical/Electronics/Computer science required
Ø At least 5-10 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts
Ø Experience in physical layer ASIC architecture, micro-architecture development, design and debug
Ø Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog
Ø Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows and scripting
Ø Knowledge in one or more of the following areas, a definite plus
o Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer)
o DSP fundamentals/Filter/FFT design/Datapath design/Error Control Coding
o Computer architecture/Processor fundamentals
Ø Preferred Qualifications:
Ø Strong knowledge of ASIC design methodologies and flows
Ø Ability to proactively take on responsibilities and competent to work in a start-up environment
Ø Worked with product development companies and having seen at least a couple of tape-outs
Ø Experience with silicon bring-up in the lab and debugging is a definite plus
Ø Experience with FPGA realizations of higher complexity designs
Ø Ability to work with teams spread across geography with excellent communication skills
Ø Candidates who have worked on DSP blocks/filters – FIRs/IIRs/FFTs/Equalizers/physical layer datapath/Error control coding (eg Viterbi/convolutional coding/LDPC/Fire code etc.)
- CAD Engineer: 5+Yrs.
Ø Candidate must be an experienced CAD/EDA engineer able to develop and enhance state-of-art Analog and mixed-signal design methodologies for advanced technology nodes to enable efficient design and development of products.
Ø The candidate would also establish collaboration with EDA vendors and work with circuit & layout design community to facilitate implementation and support of these flows.
Ø A CAD engineer who has an urge on the pulse of latest tools and programming techniques and methodologies.
Ø The candidate is not just looking to “support” CAD infrastructure but looking to enhance efficiencies and have meaningful and measurable impact of development speed and time to market.
Ø The candidate must exhibit good communications, attitude and professional relationships with various team members.
Ø BSEE/MSEE with minimum 3 years of relevant experience.
Ø Good understanding of process technologies and device physics.
Ø Good understanding of transistor level analog circuit simulation tools.
Ø Good understanding of Digital & Analog Layout.
Ø Good awareness of VLSI flow methodology RTL->GDS.
Ø Good awareness of various CAD tools including Fron-End, Verification & Back-End.
Ø Good experience of Place & Route tools (PNR/P&R) like ICC, Encounter & Innovus etc…
Ø Hands on experience of Cadence Schematic & Layout tools including ADEL/XL, Layout-XL.
Ø Hands on experience of physical verification tools like Cadence-PVS, Mentor-Calibre etc.
Ø Hands on experience with GDS tools like Calibre-DRV and/or QuickView(k2_viewer).
Ø Good understanding of physical verification ruledecks which uses PVL/SVRF.
Ø Good understanding of PDKs of various technologies ex: TSMC, GF, IBM, Intel etc…
Ø Good knowledge of Cadence-SKILL language.
Ø Good experience with programming languages like C, C++ and/or LISP etc…
Ø Solid knowledge of scripting languages like PERL, TCL, Shell (bash/ksh/tcsh) and/or Python, Ruby.
Ø Hands on experience in developing Graphical User Interfaces(GUIs) using Perl-TK/TCL-TK/Python-TK/Ruby-TK etc…
Ø Hands on experience with DRC/LVS/PEX flow methodologies including development & debugging.
Ø Good awareness of Power/EMIR tools like Apache-Totem/Voltus etc..
Ø Experience in development, maintenance and support of CAD environments for IC designs.
Ø Firm understanding of Cadence DFII.
We also have below opening with few more clients:
Salary: Guaranteed 100% hike from current salary or 30% more from the offered CTC.
Position: Permanent with a serviced based company and deputation would be at their customer location i.e. (Intel, TI, NXP, Qualcomm, Samsung, Broadcom, Rambus, ARM, LGSI, Sony etc).
About company: Fastest growing 4 years old serviced based semiconductor company.
Location: BLR/HYD/Noida/ Ahmadabad.
Experience: (3-15) Years.
- Digital:
a) SoC/ASIC Design.
b) SoC/ASIC Verification.
c) Physical Design (PnR/ STA).
d) DFT
- Memory:
a) Memory Layout/Design.
b) Memory Modelling and Verification Engineer.
- Analog/IO/IBIS:
a) RF/Analog Layout/Design
b) IO Layout/Design
c) IO Layout with FinFets
d) IBIS Models Generation
Kindly share your updated profile with below details.
• Total years of experience.
• Current CTC.
• Expected CTC.
• Notice Period.
• Any offer in hand?
1. If yes, is it from a serviced based company or a product based?
2. Please specify the offered CTC, bonus etc?
3. What is your tentative joining date?
• What is your preferred location in India?
• Share Mobile Number - In case if you don’t have updated resume please share mobile hence we could discuss over the phone and send you relevant JD along with the company name.
• Please feel free to specify preferred time slot to have a call.
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Best Regards,
Deven Kr.
Talent Acquisition
Phone: 080-50322520.
