Qualification
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BE/B Tech/MCA/M Tech/MSc
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Experience
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4 to 10 Years
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Candidate Requirement
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DFT synthesis :
· Good knowledge of Hierarchical scan synthesis with :
o Scan segmentations
o Test models
· Handle module level scan insertion.
· Handle device scan insertion with multiple clock domains.
ATPG
• Able to do Block/ Device level pattern generation and simulations.
• Scan interleaved with memory bist patterns gen and validation.
• Device level transition delay testing with multiple clocks, handling exceptions.
• Able to do Sequential ATPG with RAMs and latches, coverage analysis.
• Path Delay tests, delay coverage analysis.
• Excellent knowledge on usage of ATPG tool.-
• Able to do Silicon debug and diagnostics
• Delay tests using PLL, silicon debug and diagnostics.
BIST
• Good knowledge of On-chip scans compression or bist techniques and test time reduction.
• Memory BIST integration in SoC and verification, selecting the optimal mem.
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Work Location
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Bangalore/Cochin
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Send to me - dipanjanghoshal@yahoo.co.in if fitment there
Requirement
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Physical Design
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Job Code
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345036/345037
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Qualification
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BE/B Tech/MCA/M Tech/MSc
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Experience
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4 to 10 Years
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Candidate Requirement
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· Experience in Physical Design implementation
· Played significant role in multiple tape-outs across 90-22nm designs
· Skill Set (all or most of the below list):
o complex block implementation
o power estimation, planning and analysis (static and dynamic IR, EM)
o floor planning, placement & congestion, timing closure, CTS, post CTS flow
o PV: DRC/LVS/ GDS checks
· Proficient in industry standard EDA tool flows (SNPS or CDN)
· Optional: Low power
Responsibilities:
• Independently handle the execution and delivery of a medium to complex blocks
• RTL2GDS implementation
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Work Location
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Bangalore/Pune
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