FYI...
Hi All
Mirafra are looking for people working in Verification, Physical Verification, STA Synthesis, Post Silicon Validation, Physical design using ( Talus, ICC or SOC Encounter ). Following are the reqs.: (Detailed JDs below)
Please share your updated profile to
naveenyk@mirafra.com
1. Physical Design (Engineer/Lead/Manager, 4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
2. Verification using System Verilog (3-8 yrs.)
3. Physical Verification (4-8 yrs.)
4. IR Drop
5. Post Silicon Validation (4 -8 yrs.)
6. STA Synthesis
7. RTL Design (4 – 8yrs)
Detailed JDs
1. Physical Design Engineer/Lead/Manager (4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD activities involve , Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints management , floorplan/IR-Drop/placement/
Optimization/Timing Closure/DRC/LVS .
2. System Verilog verification.
FE verification (OVM) engineer openings,experience ranging from 4 to 8 yrs.
1. Experience in RTL verification and fundamental knowledge in basic verification concepts and issues
2. Hands on experience in RTL verification using OVM
3. Development of OVCs using System Verilog
4. Working experience in OVM verification environment building and integration
5. Developing C/C+ testcases .
6. Working knowledge on ARM based design verification, knowhow of AHB/APB bus protocols.
3. Post Silicon Validation
Processor Architecture Knowledge is a must(ARM processor knowledge is preferred). Protocol knowledge is required. Hands on exp in “C” / Assembly coding is a must. Executing Validation Test plan. Debugging skill of embedded. Should handle Oscilloscope and Logic Analyzer. Emulation knowledge is preferred.
4. Physical verification
Candidate should have 5+ yr exp in physical verification of ASIC chips having multi-million gates, in lower technology (preferably 28nm) He should be good at debugging DRC, LVS,ERC, ESD, DFM rules using industry standard layout verification tools.
He should provide Physical verification support for both full chip and block designers and develop infrastructures to automate the physical verification.
The candidate should be expect in Calibre tool and should have working knowledge of one of the scripting languages PERLTCL,SHELL.
The candidate should have good aptitude and ready to adapt and learn different domains.
5. IR Drop
Full chip RDL routing in SOC Encounter
IR drop using Redhawk
Flip chip bump placement & routing
Calibre for chip level drc/lvs
Hands-on exp. of SOC Encounter, Redhawk and Calibre tool is mandatory.
6. STA Syntesis
Candidates who are good in Design Compiler and Prime Time.
All the best
Hi All
Mirafra are looking for people working in Verification, Physical Verification, STA Synthesis, Post Silicon Validation, Physical design using ( Talus, ICC or SOC Encounter ). Following are the reqs.: (Detailed JDs below)
Please share your updated profile to
naveenyk@mirafra.com
1. Physical Design (Engineer/Lead/Manager, 4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
2. Verification using System Verilog (3-8 yrs.)
3. Physical Verification (4-8 yrs.)
4. IR Drop
5. Post Silicon Validation (4 -8 yrs.)
6. STA Synthesis
7. RTL Design (4 – 8yrs)
Detailed JDs
1. Physical Design Engineer/Lead/Manager (4-10 yrs.) with hands on experience on all aspects of RTL2GDS using ICC, Talus or SOC and multiple tapeout.
Tools : Design Compiler , ICC or Talus for PnR , Encounter for FloorPlan , Redhawk for IR-Drop, PT/PTSI , Calibre , LEC , Spyglass Activities :
Physical design of Hard Macros/Partitions of sizes upto 1000K placeable instances from RTLto GDS ,technologies varying from 45nm to 28nm . PD activities involve , Synthesis of RTL to gate netlist, Netlist level optimization , RTL to Gate LEC , scan chain hookup ,STA Constraints management , floorplan/IR-Drop/placement/
Optimization/Timing Closure/DRC/LVS .
2. System Verilog verification.
FE verification (OVM) engineer openings,experience ranging from 4 to 8 yrs.
1. Experience in RTL verification and fundamental knowledge in basic verification concepts and issues
2. Hands on experience in RTL verification using OVM
3. Development of OVCs using System Verilog
4. Working experience in OVM verification environment building and integration
5. Developing C/C+ testcases .
6. Working knowledge on ARM based design verification, knowhow of AHB/APB bus protocols.
3. Post Silicon Validation
Processor Architecture Knowledge is a must(ARM processor knowledge is preferred). Protocol knowledge is required. Hands on exp in “C” / Assembly coding is a must. Executing Validation Test plan. Debugging skill of embedded. Should handle Oscilloscope and Logic Analyzer. Emulation knowledge is preferred.
4. Physical verification
Candidate should have 5+ yr exp in physical verification of ASIC chips having multi-million gates, in lower technology (preferably 28nm) He should be good at debugging DRC, LVS,ERC, ESD, DFM rules using industry standard layout verification tools.
He should provide Physical verification support for both full chip and block designers and develop infrastructures to automate the physical verification.
The candidate should be expect in Calibre tool and should have working knowledge of one of the scripting languages PERLTCL,SHELL.
The candidate should have good aptitude and ready to adapt and learn different domains.
5. IR Drop
Full chip RDL routing in SOC Encounter
IR drop using Redhawk
Flip chip bump placement & routing
Calibre for chip level drc/lvs
Hands-on exp. of SOC Encounter, Redhawk and Calibre tool is mandatory.
6. STA Syntesis
Candidates who are good in Design Compiler and Prime Time.
All the best
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