Hi All,
We are looking for Physical Design Engineers with 1.6 to 8 years experience.
Location: Bangalore/Hyderabad
Job Description :
Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)
· Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout
· Clear understanding and command over all aspects of physical design
· Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter
· Skill and experience in scripting using Tcl or Perl desirable
Verification : (2 to 8) : (system verilog,specman,arm processor,soc) :
Skills/Experience
Minimum 2 - 8 years experience in ASIC/System verification/gate level
verification/post silicon testing.
Expertise in verifying complex designs from system as well as block level, through
design flow.
Experience in VERA, SYSTEM VERILOG, MODELSIM/VCS, Debussy
Knowledge on Perl or any other scripting language
Understanding of RTL design/verification concept
Exposure to post silicon debug – ATE testing/Bench/application testing
Note:I would really appreciate if you could voice the below openings to your friends/colleagues and others who you think may be suitable and interested in a job change.
I would also greatly appreciate if you could let me know their email id's / contact tel #'s and we will get in touch with them on our own. If you wish, we will not name you as a source of reference
Send your resumes to vuppalapatinirmala@gmail.com
regards
-Tirumala
We are looking for Physical Design Engineers with 1.6 to 8 years experience.
Location: Bangalore/Hyderabad
Job Description :
Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm & 65nm)
· Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, DFM, and tapeout
· Clear understanding and command over all aspects of physical design
· Expertise in Synopsys IC Compiler / Magma Talus / Cadence SoC Encounter
· Skill and experience in scripting using Tcl or Perl desirable
Verification : (2 to 8) : (system verilog,specman,arm processor,soc) :
Skills/Experience
Minimum 2 - 8 years experience in ASIC/System verification/gate level
verification/post silicon testing.
Expertise in verifying complex designs from system as well as block level, through
design flow.
Experience in VERA, SYSTEM VERILOG, MODELSIM/VCS, Debussy
Knowledge on Perl or any other scripting language
Understanding of RTL design/verification concept
Exposure to post silicon debug – ATE testing/Bench/application testing
Note:I would really appreciate if you could voice the below openings to your friends/colleagues and others who you think may be suitable and interested in a job change.
I would also greatly appreciate if you could let me know their email id's / contact tel #'s and we will get in touch with them on our own. If you wish, we will not name you as a source of reference
Send your resumes to vuppalapatinirmala@gmail.com
regards
-Tirumala
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