Freshers Openings with Deloitte for Hyderabad Location

Hi,

Openings for B.Tech freshers at Deloitte in ERP. If you have any aquaintance who is a B.tech fresher may send their resume to ghamsala@deloitte.com by evening. They will be called for interview tomorrow.

Thank you. For hyd location

Wish you all the best

By Unknown with 2 comments

SQL Server Administrator Openings with CERNER HEALTHCARE SOLUTIONS PVT LTD for Bangalore location

Job Title:	SQL Server Administrator
Company:	CERNER HEALTHCARE SOLUTIONS PVT LTD
Location:	Bangalore
Website:	http://www.cerner.com
Eligibility:	Any Graduate

Click to assess yourself on the required skill before applying!

Skills:	Ms Sql Server , Performance Tuning, Database Design, Database Administration
Experience:	2 - 5 Years
Job Summary:	Responsibities: The Database Administrator is responsible for the installation of the database environment and outputs. The DBA performs work on new project installations, Database release upgrades, and/or database performance management projects. Work involves interaction with end customers and Installation and Support teams, troubleshooting of customer issues, providing solutions. Build, manage and administration of database environments. MS SQL Server Database Backups/Restores, Installations /Upgradations /Migrations/Configurations, High Availability configurations, Performance Tuning, Database Design, Disaster Recovery support Work also involves interaction with end customers and Installation and Support teams, troubleshooting of customer issues, providing solutions. Work might demand extended working hours / weekend support and might require working in Shifts. Monitor & troubleshoot databases, alerts, backups and performance issues Ability to multitask and work on multiple projects simultaneously. Ability to learn new processes, tools and technologies as required. Ability to work overtime and irregular hours as and when needed. Strong organizational skills. Active team player, collaborate well with global teams. NOTE: Work might demand extended working hours / weekend support and might require working in Shifts.   Requirements: Bachelor's degree or equivalent experience 2 to 5 years of experience in providing 24x7 production database support and project implementations Strong SQL Server 2008/12/14 DBA Experience is essential Hands on experience on System DBA tasks, TSQL Programming, High Availability, Performance Tuning, Disaster Recovery, SQL Server Architecture is required. Strong technically oriented background Experience with RDBMS technologies: Predominantly in SQL Server. Knowledge on DB2 or Oracle would be an added advantage SQL Server certifications are preferred. Familiar with any change and problem management process. Experience working independently with minimal supervision. Display flexibility and openness to listen to and evaluate a variety of opinions and approaches. Requires strong English communications. Requires customer relationship skills (professional & polished). Ability to diagnose & troubleshoot problems, and suggest solutions and improvements. Soarian Knowledge a Plus. Please share your resumes to manjusha.dash@cerner.com

By Unknown with No comments

Java/Android Developer for Bangalore location

Job Title:	Java/Android Developer
Company:	India Brains Infotech
Location:	Bangalore
Website:
Eligibility:	Any Graduate

Click to assess yourself on the required skill before applying!

Skills:	Core Java , Android SDK, Javascript ,android application, iphone application
Salary:	2,50,000 - 5,50,000 P.A.
Experience:	2-4 years
Job Summary:	Responsibilities: 1.Design, develop and build the native applications for Android platform 2.Work closely with web development team (PHP) to create mobile applications linked with  3.SQL databases Requirements: 1.Minimum B.E. / B.Tech / MCA / M.Sc in Computers / IT with 4+ years of experience in Android development. 2.Strong experience in Core Java, Android SDK , Web Services, SQLite and third part APIs such as Google Map, Social media    integration 3.Icloud integration. 4.Preferably should have published one or more Android apps in the Google Play store. 5.Solid understanding of the full mobile development life cycle.

Please share your resumes to divakar@greatandhra.com

wish you all the best

By Unknown with No comments

JOB - Semiconductor (RTL2GDSII, STD CELL Layout, Physical Design, STA Synthesis, SoC/IP/ ASIC Verification). DETAILS BELOW.

Dear Reader,

Greetings … Trust you are doing well…!!!... Please spare a minute of your time & have a look below. 

We would like to introduce ourselves as Bangalore based IT Job consultant & taking care of end to end recruitment process for few of our SEMICONDUCTOR clients hence please find few job description below & let us know if you are looking forward to initiate a discussion with the top management.

If you are interested please let us know these details as well. Reason for job change, Current CTC, Expected CTC, Notice Period, Any offer in Hand (if yes pls let us know offered CTC).

Please share your resumes to asic.ramesh.kumar@gmail.com

Job Location - Bangalore, Job Type - Permanent.

1.     Standard cell layout 

Hands-on experience Standard cell layout of digital ASICs in leading edge CMOS processes 14nm, 16nm, 20nm, 10nm. 4+ years of relevant standard cell layout experience using the following tools: Cadence, Proficiency in development of various complex standard cell library development, Hands on expertise in DRC and LVS, DFM, Proficient with basic concept layout like Antenna, EM, ESD, Fingering matching techniques.
Skill language is added advantage. Good fundamental concept on Finfet, CMOS transistors
Good knowledge of semi-custom design flows.

2.     Physical Design
we are looking for an experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems. The engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools.
Fully responsible for Netlist to GDS physical design implementation of complex chips/blocks.
Fully responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team.
Fully responsible of physical implementation and schedule planning
Interact with physical and digital design teams between Singapore and Taiwan.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience
Similar company work experience
Has implemented large blocks with more than 30% area with memories.
Good at design closure (congestion, timing and physical verification)
Block/Chip PD:  exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm...). Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing methodology, constraints definition/cleanup. Desired experience using Synopsys PT
Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM.

3.     Physical Design.

>Experience in develop, support & maintain physical design flows & methodologies
>Experience in PTSI, ICC/First Encounter/EDI, Nanoroute, Calibre, StarRC, & Conformal
> Good knowledge of standard cell libraries
> Hands-on with STA, EM/IR & sign-off flows
>Expertise in handling highspeed digital design will be an added advantage.
> Minimum 4 years Hands-on experience with:
1. Floor planning, place & route, power & clock distribution, pin placement & timing constraints generation.
2. Timing convergence using high speed design techniques
3. Physical design verification.
4. Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods. Prior experience with 40nm or finer geometries.

4.     IR and EM - Years of Experience: 2 to 4 years

Domain Experience: IR and EM analysis, ESD is a good to have not mandatory.

Preferred Tool: Redhawk

Scripting Languages: TCL/Perl will be a big plus.

5.     IP Verification: 
For the position of IP Verification Engineer the following qualifications must be met:
5+ years of experience on IP Verification.
Developed the test benches using the System Verilog, UVM or Specman/eRM.
Developed the BFM/VIP using System Verilog or UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Understanding of Cache Concepts is desirable.
Knowledge of USB/PCIE/DDR protocols is preferred. 

6.     SOC Verification: 
We are looking for a SoC Verification Engineer with the Following Qualifications:
5+ years of experience on SoC Verification
Developed the test benches using the System Verilog and UVM.
Knowledge of C-based Verification is preferred
should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage goals.
Working knowledge of Power Aware RTL and Gate Level Simulation.
Understanding of ARM Core and DDR/LPDDR is preferable.
PCIe, USB, Serial Peripheral knowledge is preferred.  

7.     ASIC Verification - As a part of the verification team, Verification engineers are responsible for building the SV/UVM based Verification environment from Scratch, Verification at the IP's and SoC level.
Design and develop automation utilities and support verification activities. Senior ASIC/SoC Verification engineer needs to closely work with the Verification lead and ASIC/SoC architects in defining and developing the verification environment. Desired Skills and Experience.
o5+ years of experience on IP and/or SoC Verification
excellent knowledge of Verilog/VHDL/SV
developed the test benches using the System Verilog and UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Working knowledge of Power Aware RTL and Gate Level Simulation is preferable.
Understanding of ARM Core and DDR/LPDDR is preferable.
Knowledge of C/C++-based Verification is preferred.
High Speed interface PCIe, USB, Serial Peripheral knowledge is preferred.
oFPGA knowledge is a value add
good communication skills and Team player. 

8.     Very Good UVM Expertise with Full chip SoC Verification Experience
Knowledge on the ARM 64 bit V8 Architecture
Good Expertise on the DDR I/f and DDR Phys. Working Knowledge on the DDR3 and DDR4 Protocols  (or)
Good Expertise on the USB2.0 and USB3.0 Protocols. 

9.     RTL Design: - 5+Yrs
Requirement for RTL designers. (J.D)
looking for smart and enterprising RTL / ASIC Design Engineers with following skills:
* Hands on experience in RTL Design, Logic Design, and Micro-architecture development.
* Strong knowledge in HDL (Verilog/VHDL).
* Experience with Linting, Clock domain crossing checks required.
* Good understanding of Verification flows, including System Verilog.
* Good understanding of Synthesis, Static Timing Analysis, Equivalence Checking.
* Strong oral and written communication skills.

10.   STA Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity)


Responsibilities:

Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity).

Feel free to get in touch for more details about company.

With Regards,

Ramesh

By Tirumalarao Naidu with No comments

MUMPs opening for chennai location

Hi,

 

We are currently hiring MUMPs Developer for our Bangalore and Chennai Office.

 

Please find the JD below:

 

Work Location- Bangalore/Chennai

 

Experience-2-10 Years

 

Mandatory Skills :-

 -      Resource should have worked either  on C++ or Java or MUMPS/CACHE

-       Resource should have strong experience in OOPS concept

-       Resource will be working as a Individual contributor

-       Resource should have good attitude

-      Resource should have interest to write“Profile Scripting Language”(PSL Scripting)

-       Resource should open for both Chennai and Bangalore location

-     Experience in Banking Domain will be an added advantage

Send your resumes to pmsuga@gmail.com

Hi,

 

We are currently hiring MUMPs Developer for our Bangalore and Chennai Office.

 

Please find the JD below:

 

Work Location- Bangalore/Chennai

 

Experience-2-10 Years

 

Mandatory Skills :-

 -      Resource should have worked either  on C++ or Java or MUMPS/CACHE

-       Resource should have strong experience in OOPS concept

-       Resource will be working as a Individual contributor

-       Resource should have good attitude

-      Resource should have interest to write“Profile Scripting Language”(PSL Scripting)

-       Resource should open for both Chennai and Bangalore location

-     Experience in Banking Domain will be an added advantage

Thanks

Murali

+91 9886629318

•

•

•

 

__,_._,___

Thanks

Murali

+91 9886629318

__._,_.___

Reply via web post

•

•

•

 

__,_._,___

By Unknown with No comments

MUMPs Developer for our Bangalore and Chennai Office.

Hi,

We are currently hiring MUMPs Developer for our Bangalore and Chennai Office.

Please find the JD below:

Work Location- Bangalore/Chennai

Experience-2-10 Years

Mandatory Skills :-

 -      Resource should have worked either  on C++ or Java or MUMPS/CACHE

-       Resource should have strong experience in OOPS concept
-       Resource will be working as a Individual contributor
-       Resource should have good attitude
-      Resource should have interest to write “Profile Scripting Language”(PSL Scripting)
-       Resource should open for both Chennai and Bangalore location
-     Experience in Banking Domain will be an added advantage

Please send your resumes to pmsuga@gmail.com

Thanks

Murali

+91 9886629318

__._,_.___

By Tirumalarao Naidu with No comments

30 Mechanical diploma candidates with or without experience for BOSCH Pune location

FYI....

Dear friends,

Bosch needs 30 Mechanical diploma candidates with or without experience for BOSCH Pune location. Pls inform anybody if u know. Salary 35 to 45 k take home. 2 years bond.

Confirmation based on work efficiency after 2 years. Immediate requirement.

please forward your resume to praveen.ks@in.bosch.com

Forward it to your friends
Forwarded as received..

Wish you all the best

By Tirumalarao Naidu with 13 comments

Openings for Business Development Manager's for Johannesburg x5, Durban x2, Cape Town x1, must have sales experience, hardcore sales - use to cold calling, at least 3

 Hi There,

We are urgently looking for Business Development Manager's for Johannesburg x5, Durban x2, Cape Town x1, must have sales experience, hardcore sales - use to cold calling, at least 3 years experience. 

Travel and Tourism sales an advantage. 
Have your own transport.

These are urgent positions. 

Package: Increase on your current salary + benefits + comm. 

Should you be interested please forward your 'word' cv to LS@outsourcing-guru.co.za and add 'Business Development Manager & Area in the subject box

Wish you all the best

By Tirumalarao Naidu with No comments

Openings in Fireeye

Hi All,

There are multiple openings in Fireeye, Bangalore

Please find below the weblink and let me know if interested share the profile to

mailrajeshpillai@gmail.com

https://www.fireeye.com/company/jobs.html

-- 

Rajesh

By Tirumalarao Naidu with No comments

Openings for Dynamic HR Executive(Male) with MBA - HR Qualification from a Reputed Business School

FYI....

Hi All,

Wanted Dynamic HR Executive(Male) with MBA - HR Qualification from a Reputed Business School with good communication, interpersonal & computer skills with 0 to 1 years experience. Salary: 3 to 3.6 lakhs
Work Location: Hyderabad

 Send Resumes to gk@criska.in

Wish you all the best

By Tirumalarao Naidu with 1 comment

2 years Experienced openings for PHP,.Net,Marketing in bound and Out Bound Openings

FYI.....

Hi, 

        Job Vacancy for
           1. asp .net developer (2+ Yrs Exp).
           2. php developer (2+ Yrs Exp).

           3. Marketing in bond (Female).
           4. Marketing Out bond (Male).
           

For more details Contact : Basavaraj M (9620888105)

Wish you all the best

regards

-Tirumala

By Tirumalarao Naidu with No comments

Freshers Openings 2013 and 2014 with SQS India BFSI Ltd

By Tirumalarao Naidu with No comments

Fresher’s for Ad-Operations

Fresher’s for Ad-Operations
Category: Any graduate from 2015 batch
Background: BE(any stream),MCA
Company Name: ClearPier (www.clearpier.com)
Location : Pune
Email Id: swapnil.kosukar@clearpier.com
Please apply only if your preferred location is Pune.

Wish you all the best

By Tirumalarao Naidu with No comments

VLSI Openings

Qualification	BE/B Tech/MCA/M  Tech/MSc
Experience	4 to 10 Years
Candidate Requirement	DFT synthesis : ·         Good knowledge of Hierarchical scan synthesis with : o   Scan segmentations o   Test models ·         Handle module level scan insertion. ·         Handle device scan insertion with multiple clock domains. ATPG •        Able to do Block/ Device level pattern generation and simulations. •        Scan interleaved with memory bist patterns gen and validation. •        Device level transition delay testing with multiple clocks, handling exceptions. •        Able to do Sequential ATPG with RAMs and latches, coverage analysis. •        Path Delay tests, delay coverage analysis. •        Excellent knowledge on usage of ATPG tool.- •        Able to do Silicon debug and diagnostics •        Delay tests using PLL, silicon debug and diagnostics. BIST •        Good knowledge of On-chip scans compression or bist techniques and test time reduction. •        Memory BIST integration in SoC and verification, selecting the optimal mem.
Work Location	Bangalore/Cochin

Send to me - dipanjanghoshal@yahoo.co.in if fitment there

 

Requirement	Physical Design
Job Code	345036/345037
Qualification	BE/B Tech/MCA/M Tech/MSc
Experience	4 to 10 Years
Candidate Requirement	·         Experience in Physical Design implementation ·         Played significant role in multiple tape-outs across 90-22nm designs ·         Skill Set (all or most of the below list): o   complex block implementation o   power estimation, planning and analysis  (static and dynamic IR, EM) o   floor planning, placement & congestion, timing closure, CTS, post CTS flow o   PV: DRC/LVS/ GDS checks ·         Proficient in industry standard EDA tool flows (SNPS or CDN) ·         Optional: Low power   Responsibilities: •        Independently handle the execution and delivery of a medium to complex blocks •        RTL2GDS implementation
Work Location	Bangalore/Pune

By Tirumalarao Naidu with No comments