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We would like to introduce ourselves as Bangalore based IT Job consultant & taking care of end to end recruitment process for few of our SEMICONDUCTOR clients hence please find few job description below & let us know if you are looking forward to initiate a discussion with the top management.
If you are interested please let us know these details as well. Reason for job change, Current CTC, Expected CTC, Notice Period, Any offer in Hand (if yes pls let us know offered CTC).
Please share your resumes to asic.ramesh.kumar@gmail.com
Job Location - Bangalore, Job Type - Permanent.
1. Standard cell layout
Hands-on experience Standard cell layout of digital ASICs in leading edge CMOS processes 14nm, 16nm, 20nm, 10nm. 4+ years of relevant standard cell layout experience using the following tools: Cadence, Proficiency in development of various complex standard cell library development, Hands on expertise in DRC and LVS, DFM, Proficient with basic concept layout like Antenna, EM, ESD, Fingering matching techniques.
Skill language is added advantage. Good fundamental concept on Finfet, CMOS transistors
Good knowledge of semi-custom design flows.
Skill language is added advantage. Good fundamental concept on Finfet, CMOS transistors
Good knowledge of semi-custom design flows.
2. Physical Design
we are looking for an experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems. The engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools.
Fully responsible for Netlist to GDS physical design implementation of complex chips/blocks.
Fully responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team.
Fully responsible of physical implementation and schedule planning
Interact with physical and digital design teams between Singapore and Taiwan.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience
Similar company work experience
Has implemented large blocks with more than 30% area with memories.
Good at design closure (congestion, timing and physical verification)
Block/Chip PD: exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm...). Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing methodology, constraints definition/cleanup. Desired experience using Synopsys PT
Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM.
we are looking for an experienced Physical Design engineers to oversee the P&R process of core IPs and complex subsystems. The engineer will be responsible for owning tapeouts of Blocks/Chips and integrates implementation environment components utilizing advanced flows and latest P&R tools.
Fully responsible for Netlist to GDS physical design implementation of complex chips/blocks.
Fully responsible of signoff tasks, including power integrity, signal integrity, RC correlation and layout signoff flow in physical design team.
Fully responsible of physical implementation and schedule planning
Interact with physical and digital design teams between Singapore and Taiwan.
Technical hands-on capability and strong related P&R experience. Preferably Synopsys flows/tools
He/She should have experience in complete block level implementation (2M plus) and top level integration experience or MACRO implementation experience
Similar company work experience
Has implemented large blocks with more than 30% area with memories.
Good at design closure (congestion, timing and physical verification)
Block/Chip PD: exposure to multi-million gate design (>2million instances with 100+ memories) in recent technologies (32nm,28nm,20nm...). Desired experience using Synopsys ICC with good TCL scripting skills
Timing : should be able to drive the timing methodology, constraints definition/cleanup. Desired experience using Synopsys PT
Integration/Physical Verification: desired chip finish experience using Mentor Caliber for DRC/LVS, handling multi-million hier designs, along with good understanding of the sign-off checks, EM/IR, XTalk, DFM.
3. Physical Design.
>Experience in develop, support & maintain physical design flows & methodologies
>Experience in PTSI, ICC/First Encounter/EDI, Nanoroute, Calibre, StarRC, & Conformal
> Good knowledge of standard cell libraries
> Hands-on with STA, EM/IR & sign-off flows
>Expertise in handling highspeed digital design will be an added advantage.
> Minimum 4 years Hands-on experience with:
1. Floor planning, place & route, power & clock distribution, pin placement & timing constraints generation.
2. Timing convergence using high speed design techniques
3. Physical design verification.
4. Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods. Prior experience with 40nm or finer geometries.
>Experience in develop, support & maintain physical design flows & methodologies
>Experience in PTSI, ICC/First Encounter/EDI, Nanoroute, Calibre, StarRC, & Conformal
> Good knowledge of standard cell libraries
> Hands-on with STA, EM/IR & sign-off flows
>Expertise in handling highspeed digital design will be an added advantage.
> Minimum 4 years Hands-on experience with:
1. Floor planning, place & route, power & clock distribution, pin placement & timing constraints generation.
2. Timing convergence using high speed design techniques
3. Physical design verification.
4. Functional verification at various levels of design hierarchy with respect to golden RTL by formal methods. Prior experience with 40nm or finer geometries.
4. IR and EM - Years of Experience: 2 to 4 years
Domain Experience: IR and EM analysis, ESD is a good to have not mandatory.
Preferred Tool: Redhawk
Scripting Languages: TCL/Perl will be a big plus.
5. IP Verification:
For the position of IP Verification Engineer the following qualifications must be met:
5+ years of experience on IP Verification.
Developed the test benches using the System Verilog, UVM or Specman/eRM.
Developed the BFM/VIP using System Verilog or UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Understanding of Cache Concepts is desirable.
Knowledge of USB/PCIE/DDR protocols is preferred.
For the position of IP Verification Engineer the following qualifications must be met:
5+ years of experience on IP Verification.
Developed the test benches using the System Verilog, UVM or Specman/eRM.
Developed the BFM/VIP using System Verilog or UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Understanding of Cache Concepts is desirable.
Knowledge of USB/PCIE/DDR protocols is preferred.
6. SOC Verification:
We are looking for a SoC Verification Engineer with the Following Qualifications:
5+ years of experience on SoC Verification
Developed the test benches using the System Verilog and UVM.
Knowledge of C-based Verification is preferred
should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage goals.
Working knowledge of Power Aware RTL and Gate Level Simulation.
Understanding of ARM Core and DDR/LPDDR is preferable.
PCIe, USB, Serial Peripheral knowledge is preferred.
We are looking for a SoC Verification Engineer with the Following Qualifications:
5+ years of experience on SoC Verification
Developed the test benches using the System Verilog and UVM.
Knowledge of C-based Verification is preferred
should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage goals.
Working knowledge of Power Aware RTL and Gate Level Simulation.
Understanding of ARM Core and DDR/LPDDR is preferable.
PCIe, USB, Serial Peripheral knowledge is preferred.
7. ASIC Verification - As a part of the verification team, Verification engineers are responsible for building the SV/UVM based Verification environment from Scratch, Verification at the IP's and SoC level.
Design and develop automation utilities and support verification activities. Senior ASIC/SoC Verification engineer needs to closely work with the Verification lead and ASIC/SoC architects in defining and developing the verification environment. Desired Skills and Experience.
o5+ years of experience on IP and/or SoC Verification
excellent knowledge of Verilog/VHDL/SV
developed the test benches using the System Verilog and UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Working knowledge of Power Aware RTL and Gate Level Simulation is preferable.
Understanding of ARM Core and DDR/LPDDR is preferable.
Knowledge of C/C++-based Verification is preferred.
High Speed interface PCIe, USB, Serial Peripheral knowledge is preferred.
oFPGA knowledge is a value add
good communication skills and Team player.
Design and develop automation utilities and support verification activities. Senior ASIC/SoC Verification engineer needs to closely work with the Verification lead and ASIC/SoC architects in defining and developing the verification environment. Desired Skills and Experience.
o5+ years of experience on IP and/or SoC Verification
excellent knowledge of Verilog/VHDL/SV
developed the test benches using the System Verilog and UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Code goals.
Working knowledge of Power Aware RTL and Gate Level Simulation is preferable.
Understanding of ARM Core and DDR/LPDDR is preferable.
Knowledge of C/C++-based Verification is preferred.
High Speed interface PCIe, USB, Serial Peripheral knowledge is preferred.
oFPGA knowledge is a value add
good communication skills and Team player.
8. Very Good UVM Expertise with Full chip SoC Verification Experience
Knowledge on the ARM 64 bit V8 Architecture
Good Expertise on the DDR I/f and DDR Phys. Working Knowledge on the DDR3 and DDR4 Protocols (or)
Good Expertise on the USB2.0 and USB3.0 Protocols.
Knowledge on the ARM 64 bit V8 Architecture
Good Expertise on the DDR I/f and DDR Phys. Working Knowledge on the DDR3 and DDR4 Protocols (or)
Good Expertise on the USB2.0 and USB3.0 Protocols.
9. RTL Design: - 5+Yrs
Requirement for RTL designers. (J.D)
looking for smart and enterprising RTL / ASIC Design Engineers with following skills:
* Hands on experience in RTL Design, Logic Design, and Micro-architecture development.
* Strong knowledge in HDL (Verilog/VHDL).
* Experience with Linting, Clock domain crossing checks required.
* Good understanding of Verification flows, including System Verilog.
* Good understanding of Synthesis, Static Timing Analysis, Equivalence Checking.
* Strong oral and written communication skills.
Requirement for RTL designers. (J.D)
looking for smart and enterprising RTL / ASIC Design Engineers with following skills:
* Hands on experience in RTL Design, Logic Design, and Micro-architecture development.
* Strong knowledge in HDL (Verilog/VHDL).
* Experience with Linting, Clock domain crossing checks required.
* Good understanding of Verification flows, including System Verilog.
* Good understanding of Synthesis, Static Timing Analysis, Equivalence Checking.
* Strong oral and written communication skills.
10. STA Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity)
Responsibilities:
Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity).
Responsibilities:
Synthesis expert for ARM CPU Cores Good understanding of the synthesis/PD convergence cycle in terms of flows/scripting, synthesis, timing closure Manage IP dependencies, planning and tracking of all front end design related tasks Should possess a strong understanding of a particular technical area and has accumulated significant experience in this area and other related areas. Streamline power aware synthesis. UPF based floor-planning for complex SoCs. Place and route, verification flow. Clock tree, Synthesis, High-Speed, Physical Design, Primetime, Perl, Shell, Cadence, Floorplanning, Integration, Timing, Closure, Power Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC conformal Working knowledge of timing closure is must SoC Design (ASIC integration, peripherals, Bus Design, ASIC Design, RTL Design, DC/PC, LINT, PTSI, Verilog/VHDL) Timing Constraints & Closure (PTSI, STA, Primetime) RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency) Low Power Design (clock gating, power gating, power grids, power integrity).
Feel free to get in touch for more details about company.
With Regards,
Ramesh
